1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved structure and method for producing erasable programmable read only memory devices (EPROM's).
2) Description of the Prior Art
In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large increase due to the rapid growth of the digital electronic market with multiplying applications. Moreover, erasable programmable read only memory devices (EPROM's) are being produced in larger quantities.
There are many types of memory devices. Memory units that are frequently read from but seldom or never written into, such as the control programs in hand calculators, are known as read-only memories (ROM's). ROM's have permanent information placed in them during manufacture. Programmable ROM's (PROMs) may be manufactured as standard units and then have permanent information implanted in them by a pattern of electrical signals. Most importantly, erasable programmable ROM's (EPROM's), may have new information implanted in them from time to time by the user.
The microminiturzation of electronic devices creates the need to make higher density EPROM's. Microminiturzation increases the speed of operation and reduces production costs. However, new device structure and processing constraints emerge as EPROM's are made at higher densities.
One important EPROM constraint is the tradeoff between efficient programmability and reliable device operations. EPROM programmability is determined by successful device write and erase operations. Also, immunity to drain and read disturbances determines EPROM device reliability.
A recent improvement in EPROM device structures appears in Liu, David K. Y. et al., "Optimization of a Source-Side-Injection FAMOS Cell for Flash EPROM Applications", IEDM Tech,. Dig., 1991, pp. 315-318. Lui describes a source-side-injection FAMOS cell for an EPROM which improves upon the conventional EPROM cell. Lui describes a source side injection FAMOS cell whose high resistive region is implemented with a non-overlapped and lightly doped region at the source end. FIG. 1 shows a conventional structure as described by Lui. The convention EPROM device is built on semiconductor substrate 10 and contains a source 20, a drain 12, a floating gate 14, a control gate 16, tunnel oxide 13, and insulator 15. As shown in FIG. 1, a lightly doped source 18 is non-overlapping with the floating gate and the drain. This structure including the lightly doped source 18 is referred to as a floating-gate avalanche-injection MOS (FAMOS) cell.
A Flash EPROM cell uses Channel Hot Electron injection at the drain to perform a write operations. Also, a Flash EPROM cell uses Fowler-Nordheim tunneling at the source to constitute erase operation. The rate of write and erase operations are influenced by the strength of the electric field between the lightly doped source and the floating gate. The higher the electric field, the faster the erase and write operations.
The conventional device as described by Lui could be improved if the electric field between the source to the floating gate could be increased. A higher electric field would increase the device erase and write rates. A higher source to gate electric field would increase the Fowler-Nordheim tunneling current from the floating gate to the lightly doped source which would increase the erase rate. Also, a higher gate to source vertical electric field would increase the channel hot electron generation from the lightly doped source to the floating gate which increases the write operation rate.
The electric field between the lightly doped source and floating gate can be increased by reducing the tunnel oxide thickness. But if the tunnel oxide thickness is reduced below 80 to 120 Angstroms, pinholes in the oxide reduce device reliability and yields. Therefore, an opportunity exists to increase the electric field between the lightly doped source and the gate while maintaining yields.
A method of producing a recessed gate metal oxide semiconductor field effect transistor device (MOSFET) that seeks to reduce the source to drain leakage problem is shown in U.S. Pat. No. 5,108,937. However in this invention a recessed gate structure is formed after the source and drain are formed in a MOSFET device. The MOSFET and EPROM devices have much different structures and electrical characteristics. Therefore, U.S. Pat. No. 5,108,937 is not applicable to EPROM devices.